In certain applications, data from a plurality of Input/Output Processors (I/OPs) in a first clock domain is transferred to a Second Level Cache (SLC) in a second clock domain. The difference in data transfer rates because of the two different clock domains can cause slowdown in the data transfer. To handle the slowdown in data transfer, data buffers can be used to temporarily store the data giving the system time to catch up. While handling the temporary storage of data, the data buffers usually require numerous logic chips to provide the necessary data storage space.
In order to compensate for the different data transfer rates without storing the data in buffers, the present invention uses multiple registers to transfer data from a bridge at a rate fast enough to keep up with the transfer of data into the bridge.
The system prioritizes the transfer of data packets to ensure each of the input/output processors have equal access. With the present system, the data packets within a group of data packets are transferred by size with the longer data packets transferred from the bridge before the shorter data packets. After transfer of the longer data packets, the shortest data packets in the group of data packets are grouped together to fill the interface registers and are then transferred from the bridge to the cache during a single transfer cycle.